1. Field of the Invention
Generally, the present disclosure relates to the field of semiconductor manufacturing, and, more particularly, to the formation of contact structures connecting circuit elements to interconnect structures of the first metallization level.
2. Description of the Related Art
Semiconductor devices, such as advanced integrated circuits, typically contain a great number of circuit elements, such as transistors, capacitors, resistors and the like, which are usually formed in a substantially planar configuration on an appropriate substrate having formed thereon a crystalline semiconductor layer. Due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements may generally not be established within the same level on which the circuit elements are manufactured, but require one or more additional “wiring” layers, which are also referred to as metallization layers. These metallization layers generally include metal-containing lines, providing the inner-level electrical connection, and also include a plurality of inter-level connections, which are also referred to as “vias,” that are filled with an appropriate metal and provide the electrical connection between two neighboring stacked metallization layers.
Due to the continuous reduction of the feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, that is, the packing density, also increases, thereby requiring an even larger increase in the number of electrical connections to provide the desired circuit functionality, since the number of mutual connections between the circuit elements typically increases in an over-proportional way compared to the number of circuit elements. Therefore, the number of stacked metallization layers usually increases as the number of circuit elements per chip area becomes larger, while nevertheless the sizes of individual metal lines and vias are reduced. Due to the moderately high current densities that may be encountered during the operation of advanced integrated circuits, and owing to the reduced feature size of metal lines and vias, semiconductor manufacturers are increasingly replacing the well-known metallization materials, such as aluminum, by a metal that allows higher current densities and, hence, permits a reduction in the dimensions of the interconnections. Consequently, copper and alloys thereof are materials that are increasingly used in the fabrication of metallization layers due to the superior characteristics in view of resistance against electromigration and the significantly lower electrical resistivity compared to, for instance, aluminum. Despite these advantages, copper also exhibits a number of disadvantages regarding the processing and handling of copper in a semiconductor facility. For instance, copper readily diffuses in a plurality of well-established dielectric materials, such as silicon dioxide, wherein even minute amounts of copper, accumulating at sensitive device regions, such as contact regions of transistor elements, may lead to a failure of the respective device. For this reason, great efforts have to be made so as to reduce or avoid any copper contamination during the fabrication of the transistor elements, thereby rendering copper a less attractive candidate for the formation of contact plugs, which are in direct contact with respective contact regions of the circuit elements. The contact plugs provide the electrical contact of the individual circuit elements to the first metallization layer, which is formed above an inter-layer dielectric material that encloses and passivates the circuit elements.
Consequently, in advanced semiconductor devices, the respective contact plugs are typically formed of a tungsten-based metal in an inter-layer dielectric stack, typically comprised of silicon dioxide, that is formed above a so-called contact etch stop layer, which may typically be formed of silicon nitride. Due to the ongoing shrinkage of feature sizes, however, the respective contact plugs have to be formed within respective contact openings with an aspect ratio which may be as high as approximately 10:1 or more, wherein a diameter of the respective contact openings may be about 80 nm or even less for transistor devices of the 45 nm technology and beyond. The aspect ratio of such openings is generally defined as the ratio of the depth of the opening to the width of the opening. Sophisticated etch and deposition techniques may be required for forming the contact plugs, as will be described with reference to FIGS. 1a-1c in more detail.
FIG. 1a schematically illustrates a top view of a portion of a semiconductor device 100. The semiconductor device 100 comprises a substrate (not shown in FIG. 1a, 101 in FIG. 1b) above which is formed a semiconductor layer in and above which circuit elements, such as transistors, capacitors, resistors and the like, are formed. For convenience, circuit elements in the form of transistors 150a, 150b are illustrated, wherein transistor 150b is illustrated partially. The transistors 150a, 150b may comprise a gate electrode structure 151, sidewalls of which may be covered by a spacer element 152. Drain and source regions 153 are provided laterally adjacent to the gate electrode structures 151, which may be, in addition to a channel region, located below the gate electrode structures 151 and may represent an active region in the corresponding semiconductor layer. The active region may be defined by an isolation structure 102, above which also a portion of the gate electrode structures 151 may be positioned, thereby defining a gate contact region 154 which is connected to a contact plug or contact element 110 formed thereon. Similarly, contact elements 111 may be provided above contact regions 155 formed in the drain or source regions to improve the electrical characteristic of the contact. Therefore, the contact regions 155 typically comprise silicide material. It should be appreciated that the contact elements 110, 111 are typically formed in an appropriate interlayer dielectric material which, for convenience, is not shown in FIG. 1a. 
FIG. 1b schematically illustrates a cross-sectional view along the line Ib as shown in FIG. 1a, wherein the semiconductor device 100 is illustrated in a further advanced manufacturing stage. As shown, the semiconductor device 100 comprises a substrate 101 which represents any appropriate carrier material, such as a silicon substrate, a silicon-on-insulator (SOI) substrate and the like. A silicon-based semiconductor layer 103 is formed above the substrate 101. The isolation structure 102, for instance in the form of a trench isolation, defines the active region 104 in which the drain and source regions 153 are positioned, i.e., respective dopant concentrations, so as to define respective PN junctions with the remaining portion of the active region 104. Furthermore, metal silicide regions may be formed in the drain and source regions 153, thereby defining a contact region 155 thereof, and on the gate electrode structure 151, thereby defining a respective contact region 154 (FIG. 1a) for contacting the gate electrode structure 151. The metal silicide may comprise, e.g., cobalt, titanium, nickel and the like. Furthermore, the semiconductor device comprises an interlayer dielectric material 115 which typically comprises two or more dielectric layers, such as the layer 115a, which may represent a contact etch stop layer comprised of silicon nitride, and a second dielectric material 115b, for instance provided in the form of a silicon dioxide material. Typically, a thickness 115t of the interlayer dielectric material 115 is in the range of several hundred nanometers (nm) so as to obtain a sufficient distance between the gate electrode structure 151 and a first metallization layer 120 in order to maintain the parasitic capacitance at a required low level. Consequently, the contact element 111 connecting to the drain or source contact region 155 may have a moderately high aspect ratio, since the lateral size thereof is substantially restricted by the lateral dimension of the drain and source regions 153, while the depth of the contact element 111 is determined by the thickness 115t of the interlayer dielectric material 115. On the other hand, the contact element 110 (FIG. 1a) merely has to extend down to the top surface of the gate electrode structure 151, i.e., to the contact portion 154, while also the lateral dimension of the contact element 110 may be different compared to the element 111, depending on the size and shape of the contact portion 154. The contact elements 110, 111 typically may comprise a barrier layer 113, e.g., in the form of a titanium liner, followed by a titanium nitride liner, while the actual fill material 114 may be provided in the form of a tungsten material.
The metallization layer 120 typically comprises an etch stop layer 123, for instance in the form of silicon nitride, silicon carbide, nitrogen-enriched silicon carbide and the like, on which may be formed an appropriate dielectric material 124, such as a low-k dielectric material having a relative permittivity of 3.0 or less. Moreover, respective metal lines 121, 122 are formed in the dielectric material 124 and connected to the contact elements 111, 110, respectively. The metal lines 121, 122 may comprise a copper-containing metal in combination with an appropriate barrier material 125, such as a material comprising tantalum, tantalum nitride and the like. Finally, a cap layer 126 is typically provided so as to confine the copper material in the metal lines 121, 122, which may be accomplished on the basis of dielectric materials such as silicon nitride, silicon carbide and the like.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1b may comprise the following processes. After forming the circuit elements 150a, 150b on the basis of well-established techniques in accordance with design rules of the respective technology node, which includes forming an appropriate gate insulation layer and patterning the same along with the gate electrode structure 151 by sophisticated lithography and etch techniques. The drain and source regions 153 may be formed by ion implantation, using the spacer structure 152 as an appropriate implantation mask. After any anneal cycles, the metal silicide of the contact regions 154, 155 are formed and the interlayer dielectric material is deposited, for instance, by forming the contact etch stop layer 115a, followed by the deposition of silicon dioxide material on the basis of plasma enhanced chemical vapor deposition (CVD) techniques. After planarizing the resulting surface topography of the silicon dioxide material, a photolithography sequence may be performed on the basis of well-established recipes, followed by anisotropic etch techniques for forming contact openings extending through the interlayer dielectric material 115 so as to connect to the contact region 154 (FIG. 1a) of the gate electrode structure 151 and to the contact region 155 of the drain and source regions 153. During the respective etch process, sophisticated patterning regimes may be required due to the high aspect ratio of the corresponding contact opening, in particular for the contact element 111. During the complex etch sequence, the layer 115a may be used as an etch stop layer for etching the silicon dioxide material 115b, after which a further etch process, e.g., an anisotropic reactive ion etch process, may be performed in order to finally expose the contact regions of the drain and source regions 153 and of the gate electrode structure 151, i.e., the metal silicide regions 154, 155. Generally, a certain amount of over-etching is required in this etch step to reliably remove the material of the contact etch stop layer 115a in the contact region. Afterwards, typically, a wet chemical cleaning process is performed to clean the sidewalls of the obtained openings and the silicide surface at the bottom of the opening. As is well known, during complex plasma assisted etch processes, a plurality of etch by-products may be generated, at least some of which may also deposit on exposed surface areas and which may have to be removed prior to a subsequent deposition of material, such as a conductive barrier material, within the contact opening. Consequently, respective wet chemical etch recipes may be applied, such as diluted hydrofluoric acid, ammonia peroxide mixtures and the like, which are appropriate to serve as efficient recipes for conditioning exposed surface portions prior to the further processing of the device 100.
Next, the barrier layer 113 may be formed on the basis of, for instance, physical vapor deposition (PVD), such as sputter deposition. The term “sputtering” describes a mechanism in which atoms are ejected from a surface of a target material that is itself hit by sufficiently energetic particles. Sputtering has become a frequently used technique for depositing tantalum, titanium, tantalum nitride, titanium nitride and the like due to the superior characteristics compared to, for instance, CVD techniques with respect to controlling layer thickness. Additionally, exposed surfaces may inherently be cleaned by performing a sputtering without providing a deposition species. Barrier layer 113 may comprise a titanium nitride liner and a titanium layer formed thereon by sputter deposition so as to accomplish a reliable coverage of all exposed surface portions of the contact opening. The titanium nitride liner may enhance the adhesion of the titanium layer, thereby enhancing the overall mechanical stability of the contact elements 110, 111. Thereafter, the tungsten material 114 may be deposited by CVD in which tungsten hexafluorine (WF6) is reduced in a thermally activated first step on the basis of silane and is then converted into tungsten in a second step on the basis of hydrogen. During the reduction of the tungsten on the basis of hydrogen, a direct contact to silicon dioxide of the layer 115b is substantially prevented by the barrier layer 113 in order to avoid undue silicon consumption of the silicon dioxide.
Thereafter, the metallization layer 120 may be formed by depositing the etch stop layer 123 followed by the deposition of the dielectric material 124. Next, respective trenches are formed in the dielectric material 124 according to well-established single damascene strategies. Next, metal lines 121, 122 may be formed by depositing a barrier layer 125 and filling in a copper-based material, for instance on the basis of electroplating, which may be preceded by the deposition of a copper seed layer. Finally, any excess material may be removed, for instance, by chemical mechanical polishing (CMP), and the cap layer 126 may be deposited.
Subsequently, the device may be accomplished by adding further metallization layers and a contact pad layer providing a bond pad layout allowing for connecting the device to an appropriate carrier substrate providing a corresponding bond pad layout.
The conventional contact plug manufacturing process as described above provides reliable contacts for devices having a sufficient contact spacing. In semiconductor devices of the 45 nm technology, and in particular of the 32 nm technology, however, the conventional contact plug manufacturing process is considered as adversely affecting the device performance or even as substantially contributing to the overall yield loss as the inventors recognized that contact extensions 117 may be formed which may even cause shorts 118 between neighboring contacts 111.
Due to the ongoing shrinkage of feature sizes, not only the dimensions of the respective contact plugs are reduced as set forth above but also the distance to neighboring contacts and to adjacent gate electrodes. The latter is of particular relevance in regions of semiconductor devices which may comprise a plurality of closely spaced transistors. A typical spacing (gate pitch) of closely spaced transistors for devices of the 45 nm technology is approximately 160 nm and approximately 120 nm for devices of the 32 nm node.
FIG. 1c schematically illustrates a cross-sectional view in which the semiconductor device 100 may comprise a plurality of closely spaced transistors 150, each of which may comprise a corresponding gate electrode structure 151, as described above with reference to FIGS. 1a and 1b. The transistors 150 may be contacted by means of the contact elements 111, wherein, in sophisticated applications, the lateral dimension 111w of these contact elements is comparable to the space between the closely spaced gate electrode structures 151 including the spacer elements 152 and the contact etch stop layer 115a. Thus, in particular, the risk of formation of shorts 116 to gate electrode structures 151—which may substantially contribute to the overall yield loss—is increased in regions of semiconductor devices which may comprise a plurality of closely spaced transistors of the 45 and 32 nm technology and in particular following technologies having a gate spacing of 100 nm or even less.
Consequently, providing the conventional contact elements 111 may result in significant yield losses due to the formation of contact extension regions 117 and shorts 116, 118 in sensitive device areas.
In view of the situation described above, the present disclosure relates to manufacturing techniques and semiconductor devices in which formation of contact plugs does not unduly contribute to the overall yield loss.